Circuit boards comprise from one to many resin layers. Conductor assemblies are embedded in these layers and typically have a large number of spatially closely located conductor paths or networks, which may or may not have branch points. In the manufacture of circuit boards, it is important to test these embedded conductor assemblies to ensure that they have been properly formed so that the electronic device constructed from the circuit board will operate properly.
German Patent Document DE 34 08 704 A1 discloses an apparatus for testing conductor assemblies of a circuit board in which the individual networks are tested using a resistance and capacitance test. The results obtained from this test are then compared to reference values from a conductor assembly that is known to have no faults. Deviations between the test results and the reference values from the faultless conductor assembly are indicative of the existence of a fault in the tested conductor assembly. The nature and location of the fault in the defective network may be then determined. This testing method has a proven record of success in view of that fact that the test itself is easy and fast to implement and permits reliable fault detection.
Aspects of this faultless conductor assembly test method, however, are complicated. The reference values may only be established by performing resistance and capacitance tests on a faultless conductor assembly, a so-called "golden board". Producing these golden boards is complicated and expensive and is not cost effective in case of many modern circuit boards that have high conductor path or network densities.
Due to the drawbacks associated with the faultless conductor assembly testing method, learning routines have been developed in which several identical conductor assemblies are tested. The resistance and capacitance test for selected conductor paths in the various conductor assemblies are compared to each other. Using these multiple tests coupled with complicated statistical evaluation, reliable reference values may be generated.
In order to avoid some of the drawbacks associated with the learning routine testing method, attempts have been made to compute the reference values from design software. These computations, however, necessitate substantial computer capacity. Moreover, in the case of systematic errors in the production of the circuit boards, the computed reference values may deviate from the actual reference values for the circuit boards.
European Patent Document EP 0 508 062 B1 discloses a method for testing electrical conductor assemblies in which elongated electrodes are arranged on the surface of the circuit board containing the conductor assemblies. These elongated electrodes are referred to as "antennas". Alternatively, in some situations, it is possible to use certain networks of the conductor assembly as antennas for testing of the other networks of the assembly. In this case, the external elongated electrodes are not necessary. A total of n antennas A.sub.1 -A.sub.n are used to test a selected one of the networks N in the conductor assembly.
According to this test method, a complex input voltage U.sub.0 is applied to a selected one of the antennas A.sub.i. The remaining antennas A.sub.1 -A.sub.i-1 and A.sub.i+1 -A.sub.n are connected to ground (GND). Between the network N and the antenna A.sub.i exists the complex resistance, i.e., impedance, Z.sub.i =Z.sub.iR +iZ.sub.iI, and between the remaining antennas A.sub.1 -A.sub.i-1 and A.sub.i+1 -A.sub.n and the network N the complex resistance Z-Z.sub.i, where Z is the complex total resistance between all antennas and the network N. The impedances for network N are determined by detecting the complex voltage U.sub.i =U.sub.iR +iU.sub.iI with a probe that typically has its own capacitance C.sub.p.
The complex input voltage U.sub.0 =U.sub.0R +U.sub.0I comprises a constant DC voltage component and an AC voltage component having a specific frequency 2 .pi..omega.. This input voltage U.sub.0 is applied to each of the antennas in turn. The test result, the voltage U.sub.i induced in network N, is sensed each time. The resulting set of test results U.sub.1 -U.sub.n forms a data field, the values of which represent a "finger print" typically for the network N. This testing method is termed a field test.
As a general rule, the data fields of the various networks of a circuit board should differ. When the data fields of two networks are similar or identical, a short-circuit may exist between these two networks. The existence of the potential short-circuit may then be confirmed by a conventional short-circuit test in which the electrical resistance between these two networks is sensed. These short-circuit tests need to be implemented only on pairs of networks that have identical data fields. Therefore, the number of these short-circuit tests is small, as compared to similar testing methods. Testing for open-circuits is performed with a resistance test in which electrodes at the ends of the networks sense the resistance through the networks or by comparing the data field to a reference field.
The field test testing method may also be used in combination with resistance test. The short-circuit test is performed between every one of the individual networks. And, a resistance test is used to detect open-circuits for every one of the networks. Accordingly, no reference values or reference fields are needed. This approach simplifies the testing method substantially since no golden boards or other methods for determining reference values are required. Each and every conductor path or network, however, must be individually tested, which makes this field test testing method relatively tedious.
In summary, by employing reference fields, the field test testing method is substantially accelerated since only those networks that have data fields that do not agree with the reference fields must be tested. The problem still exists, however, in establishing these reference values or the reference fields.